Received: 29 January 2022 Revised: 2 September 2022 IET Power Electronics Accepted: 8 October 2022 DOI: 10.1049/pel2.12409 ORIGINAL RESEARCH Single source self-balanced switched-capacitor multilevel inverter with reduced number of semiconductors Mohammad Amani1 Milad Niaz Azari1 1 Department of electrical engineering, University of Science & Technology of Mazandaran, Behshahr, Iran 2 Faculty of Technology and Engineering, University of Mazandaran, Pasdaran Street, Babolsar, Iran Correspondence Milad Niaz Azari, Assistant Prof., Department of Electrical Engineering, University of Science and Technology of Mazandaran, P.O. Box 48518–78195, Behshahr, Iran. Email: miladniazazari@mazust.ac.ir 1 Mohammad Rezanejad2 Abstract Recently, the demand for switched-capacitor converters has increased due to the use of a low voltage input source. This article aims to improve some weak points of these inverters, such as the high number of elements by presenting a novel single-source high step-up multi-level inverter topology. The proposed inverter consists of a switched-capacitor cell with self-balancing capability. The proposed converter uses a low voltage DC source to charge a series of capacitors stage by stage to increase the amplitude of the capacitors multiple times the input voltage. These capacitors which work as asymmetrical sources can generate a high-amplitude AC output voltage level and hence reduce the number of DC sources and semiconductors which leads to the simplicity of structure. Since the proposed converter is using low voltage single DC source it can be used in a renewable energy application. Another aspect of this converter is producing negative levels in the output voltage without using a high-voltage full-bridge inverter and reducing the number of components. To verify the proposed multi-level inverter operation, a 9-level prototype is simulated in MATLAB/Simulink and implemented in the laboratory. The simulation and test result of the inverter confirm the validity of the proposed scheme. INTRODUCTION The inherent advantages of multilevel inverters (MLIs) such as reduced dv/dt stresses, near-sinusoidal output voltage waveforms, and operation with a low switching frequency, have attracted the wide attention of industrial and research communities [1]. Conventional MLIs including neutral-point- clamped (NPC), flying capacitor (FC) and cascaded H-bridge (CHB) have been widely used for motor drivers, renewable energies, microgrid applications etc. However, FC and NPC are facing challenges like capacitors’ voltages balancing and a high number of semiconductors, which is intensified by increasing the number of levels [2–5]. Also, one disadvantage of the CHB is using several isolated sources [6]. In addition, a common disadvantage between all of the above-mentioned circuits is that they are not capable of boosting input voltage which is essential for many applications such as electric vehicles (EVs) and interconnection of renewable energy systems (such as photovoltaic cells) to the grid [7, 8]. One of the simplest ways to increase the voltage amplitude is to use an inductor or transformer. However, using magnetic cores leads to increasing cost, volume, and EMI in a circuit. In recent years, one of the main orientations in power electronics has been the development of switched-capacitor (SC) inverters without inductors and transformers [1]. These converters can be used in converting the input DC voltage to AC output voltage with greater voltage amplitude, which is conducted by the capacitors. Some advantages of these singlesource converters are low weight and reduction of the harmonic contents [1]. Different structures of SCMLIs are presented in refs. [9] and [10]. A high number of switches and capacitors is one of the problems of these converters which leads the volume, size, and cost of the system to increase. Ref. [11] is a switched-capacitor inverter with a high voltage input source that is only capable of producing output voltage levels by dividing the input voltage between capacitors. Therefore, it is not able to boost the input voltage to a higher amplitude. Ref. [12] present an SCMLI converter that is capable of producing positive and negative voltage This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2022 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology. IET Power Electron. 2023;16:575–583. wileyonlinelibrary.com/iet-pel 575 AMANI ET AL. 576 levels using four isolated sources without needing a full-bridge circuit. The remarkable point regarding mentioned converter is that in the case of generating more output levels, the number of power electronic semiconductors and isolated sources increases. Ref. [13] present two types of single-source switched-capacitor MLIs. The number of switches and their drivers is high. Marxbased topologies which are called Marxiplier presented in ref. [14] are an enhanced version of the traditional Marx topology. Unlike Marx topology, the Marxiplier can increase the amplitude of the capacities which helps to boost the low voltage of the input source to a high voltage in the output. However, the complex structure for producing high voltage levels is one of the drawbacks of the presented topology. In this paper, a new single-source high step-up SCMLI is presented. The proposed MLI uses a low voltage DC input source to charge the capacitors multiple times of the input source amplitude. Therefore, the capacitors of the proposed topology work like an asymmetrical DC source. This feature allows the converter to reduce the number of isolated DC sources and the volume of the structure. The switches of the proposed converter are operating at a low switching frequency. The proposed circuit is capable of self-balancing the capacitors’ voltage and generating negative voltage levels without any need for the highvoltage full-bridge circuit. A comparison between the proposed circuit and other similar circuits indicates that the number of switches, capacitors, and total standing voltage (TSV), is lower in the proposed circuit. The paper is written below: The circuit operation principles, capacitors’ charging method, and output level production would be explained in the Section 2. The calculation of the capacitor’s capacitance is brought in Section 3 and the modulation strategy is presented in Section 4. A comparative study of the proposed circuit with the other similar circuits is conducted in Section 5. The simulation and experimental results for a 9-level prototype are presented in Section 6, and the conclusions are presented in section 7. FIGURE 1 The proposed circuit topology FIGURE 2 Capacitors’ charging path 2 CIRCUIT TOPOLOGY AND OPERATING SYSTEM 2.1 Circuit topology The structure of the proposed converter is shown in Figure 1. It consists of two half-bridge (HB) inverters (RHB (right half bride [Sun , Sdn ]) and LHB (left half bridge [Su1 , Sd1 ]) for the right and left sides of the converter) and m modified switchedcapacitor cells (SCC) which are connected in series in the middle of the topology. The proposed converter is capable of charging the capacitors located in the SCCs more than the input voltage amplitude. The voltages produced by SCCs are transferred to the load terminals through lateral (RHB and LHB) HBs. Each SCC includes four capacitors (Cu , Cd ), six power switches (Su , Sd ), and two power diodes (Du , Dd ). The proposed topology is a voltage booster in a way that the maximum output voltage can be increased depending on the number of cells. The creation of bipolar output voltage without requiring a high-voltage full-bridge inverter is another benefit of the proposed converter. These features make the converter appropriate to perform in medium high-power applications with low input voltage sources. 2.2 The capacitor’s charging process The charging modes of the capacitors are brought in Figure 2. According to Figure 2(a), it can be seen that when switch S3 is on, capacitors C1 and C2 begin to charge through diode D1 . Also based on Figure 2(b), it is evident that when the switch S2 AMANI ET AL. 577 TABLE 1 Switching modes and the capacitors charging process of the proposed 9-level circuit Level S1 S2 S3 S4 S5 S6 S7 S8 C1 C2 C3 C4 2VDC 0 1 0 1 0 0 1 0 – – + + 1.5VDC 0 0 1 0 0 0 1 0 – + + NC 1VDC 0 1 0 0 1 0 1 0 + + NC NC 1 0 0 1 0 0 1 0 – – + + 1 0 1 0 0 1 1 0 – + + NC 0.5VDC 1 0 0 0 0 1 1 0 – – – NC 0 1 0 0 0 1 0 1 0 + + NC NC 0 1 0 1 0 0 0 1 NC NC + + −0.5VDC 0 1 1 0 0 1 0 1 NC + + – −1VDC 0 1 1 0 0 0 0 1 NC – – – 1 0 0 1 0 0 0 1 NC NC + + 0 1 0 0 1 0 0 1 + + – – −1.5VDC 1 0 1 0 0 1 0 1 NC + + – −2VDC 1 0 0 0 1 0 0 1 + + – – is on, capacitors C3 and C4 begin to charge through diode D2 . And when one of the bidirectional switches S1 and S4 are conducting, the capacitors in the middle, i.e. C2 , C3 , charges which are shown in Figure 2(c). This causes an additional mode for the capacitors in the middle to be fully charged. Therefore, by ignoring voltage drop in the charging paths, the voltage across each capacitor is obtained as follows: Vcu = Vcd = 0.5 × 2i−1 × VDC i = 1, 2 … , m (1) where i is the number of SCCs and VDC refers to the input voltage. The capacitors are discharged across the load, which would be demonstrated in the next subsection. To prevent excessive voltage, and drop of the capacitors at discharging times, capacitance calculations would be presented in Section 3 to restrict the capacitors’ voltage ripple to an acceptable range. Thereby, the proposed topology does not require a closed-loop controlling method or additional circuit balancer for balancing capacitors voltage. 2.3 Generating output voltage levels In this section, the generation of the output voltage levels is specified for a 9-level converter. Switching states and associate output voltage levels are shown in Table 1. As it can be seen from Table 1, the proposed inverter is capable of increasing voltage up to 2 times of the input voltage. Figure 3 shows the switching state of the proposed converter for producing output voltage levels. According to this figure, it is evident that the proposed converter is capable of simultaneous charging of the capacitors while producing voltage levels in the output, the current path of charging the capacitors while producing voltage levels in the output is shown in a different colour where black and red are representing discharging and charging the capacitors, respectively. It can be seen from Table 1 that the proposed structure utilizes redundant switching modes to generate voltage levels. This feature allows selections of appropriate switching methods to reduce switching loss. Also,“+” and “−” show capacitors’ charging and discharging state, ‘’NC" indicates that no change happened in capacitors’ voltage. 3 3.1 CALCULATION OF CAPACITANCE Capacitance calculation Capacitors’ voltage ripple should be at a certain standard range. The lower the amount of voltage ripple, the lower the amount of power loss and the higher the capacitors’ efficiency [14]. To calculate the capacitance of the capacitors the maximum discharge should be considered. Based on Table 1 and Figures 3 and 4, the maximum discharging time for each capacitor in the proposed inverter could be obtained. Due to the half-wave symmetry of the working cycles of up and down capacitors, the calculated time for the up capacitors also applies to the down capacitors. Therefore, the maximum discharging value for each capacitor is calculated as below [14]: t2 QC = ∫ ( ) ILoad Sin 2𝜋Freft dt (2) t1 In which [t1 −t2 ] is the maximum discharging time of each capacitor, and ILoad is the maximum load current. (t1 −t8 ) can be calculated as follows [14]: Sin−1 ti = ( mAt Aref 2𝜋Fref ) i = 1, 2, 3, 4 (3) AMANI ET AL. 578 FIGURE 3 Equivalent states of the proposed converter for different output voltage levels (a) 0VDC , (b) +0.5VDC , (c) +1VDC , (d) +1.5VDC , (e) +2VDC , (f) −0.5VDC , (g) −1VDC , (h) −1.5VDC , (i) −2VDC ti = 𝜋 − Sin−1 ( 2𝜋Fref mAt Aref ) i = 5, 6, 7, 8 (4) In the above equations, Fref and Aref each are representative of the reference frequency and reference sinusoidal waveform amplitude, respectively. Considering K as the maximum capacitor voltage ripple (the standard value is 10%), the appropriate amount of capacitance is obtained from the following relation [14]: C ≥ 4 FIGURE 4 Time intervals for calculations of capacitors ΔQc KVDC (5) MODULATION STRATEGY To reduce the switching frequency of the switches used in the main circuit, nearest level control (NLC) modulation is used to generate the switching pulses. In this method, the processor (microcontroller) constantly compares the reference sinusoidal waveform with the switching states and selects the nearest AMANI ET AL. TABLE 2 579 Comparison of the proposed circuit with refs. [9–14] Comparing item [9] NL−2 Number of switches 8[ Number of diodes 14[ 8 + 1] NL−2 8 NL−2 + 1] + 1] [10] [11] NL NL ([ ([ 2 NL 2 ] × 2) + 4 [ ] × 2) + 4 7 + ([ Number of capacitors 3[ TSV (×VDC ) 17[ Number of DC source 1 Negative level With H bridge With H bridge FIGURE 5 levels 8 NL−2 8 + 1] 8 ]×7−[ NL NL 8 ([ [(NL − 1) ÷ 2] + 1 NL + ([ [ [(NL − 1) ÷ 2] × 6 [ NL NL 8 8 ] ] + 1) × 2 ] + 1) × 3 - 8 NL 8 NL 6 [13] NL NL ([ ([ 12 NL 12 ]+1)*10 ([ ]+1)*10 ([ - ] × 10) + ([ ([ NL 12 ]+1)*20 ([ 12 NL 12 NL 12 NL 12 [14] Proposed ]+1)*10 8 + [4(m)] 4+([log2 (NL ) − 2]) × 6 ]+1)*14 10 + [8(m)] 4+([log2 (NL ) − 2]) × 8 ]+1)*4 2 + [3(m)] [log2 (NL ) − 2]) × 4 ]+1)*28 8+ With H bridge ([ NL 12 ]+1)*4 1 ∞ ∑ [4(2m + 1)] 5×2[log2 (NL )−1] − 1 m=0 ] ]+1 1 Without H bridge With H bridge Without H bridge 1 Without H bridge Comparative studies: (a) the number of switches, (b) the number of diodes, (c) the number of capacitors, (d) and TSV in terms of the number of voltage level to the reference waveform. Figure 4 shows the switching waveform for each switch. 5 [12] COMPARATIVE STUDY To illustrate the effectiveness of the proposed converter, Table 2 displays a comparison between the proposed structure and the conventional inverters presented in recent years. In this comparison, the number of semiconductors, the number of DC links, the total voltage stress of the switches, and the generation of negative levels for a NL -level converter are considered. Considering Figure 5, it can be seen that the proposed circuit has applied a lower number of semiconductors in compari- son with other conventional converters. Figure 5(a–d) show the number of switches, the number of diodes, the number of capacitors, and the total standing voltage (TSV) of the switches up to 51 levels, respectively, which is representative of the appropriate performance of the proposed circuit. 6 SIMULATION AND EXPERIMENTAL VERIFICATION 6.1 Simulation results To verify the performance of the proposed converter, the simulation results are carried out using MATLAB for a AMANI ET AL. 580 The proposed 9-level inverter parameters in simulation and TABLE 3 experiment Parameters Simulation Experimental Source 24 V 24 V Switches MOSFET MOSFET(6N80) Diode Diode DIODE (MUR860) Switching frequency 50 Hz 50 Hz C1 , C2 , C3 , C4 560 µF 560 µF Resistive load 300 Ω 300 Ω Resistive-inductive load 300 Ω + 350 mH 300 Ω + 350 mH SCOPE – MEGATEK GW insteak FIGURE 7 Simulation results, (a) resistive load (ZL = 300 Ω), (b) resistive-inductive load (ZL = 300 Ω + 350 Mh) FIGURE 6 Main capacitor’s voltage in simulation 9-level inverter with the parameters of Table 3. Figure 6 shows the capacitors’ voltages which remain in an acceptable range without any closed loop control. Figure 7(a,b) show the output voltage and current under the R and RL load, respectively. Also, the total harmonic distortion (THD) of the output voltage is 4.17% without using any filter. Figure 8 shows the voltage waveform on each switch. 6.2 Experimental results To verify the performance of a 9-level MLI, a laboratory sample of the proposed converter (Figure 9) was implemented according to the parameters of Table 3. Output voltage and current waveforms with the pure resistive and inductive-resistive FIGURE 8 VDS (drain–source voltage) on each switch AMANI ET AL. FIGURE 9 581 The laboratory prototype of the proposed converter FIGURE 10 Voltage and current waveform for resistive load in experimental (ZL = 600 Ω) FIGURE 12 The voltage of main capacitors in experimental test 7 LOSSES CALCULATIONS AND EFFICIENCY COMPARISON FIGURE 11 Voltage and current waveform for resistive-inductive load in experimental (ZL = 600 Ω + 340 Mh) loads are shown in Figures 10 and 11 respectively. It can be observed that the proposed inverter can increase the source voltage magnitude from 24 to 48 V. Capacitors’ voltage is shown in Figure 12. Moreover, the Drain-Source voltage of some switches of the converter is shown in Figure 13. Also, the achieved experimental voltage THD is 4.49 which is close to the simulation one. In general, in a switched capacitor converter, three types of power loss are considered which include: switching loss (PSW ), conduction loss (PCond ), and power loss caused by capacitors voltage ripple (PRip ). Note that the maximum power losses occur in the output resistive load. Therefore, the calculations are carried out for pure resistive load. The conduction loss occurs due to parasitic impedances of the circuit component including internal on-state resistance of switches (Ron,SW ) and diodes (Ron,D ). The switching loss of a switch is due to the overlap of its voltage and current when its state changes. There is a transition time (ton or toff ) until the switch is fully turned on or off. During the transition period, AMANI ET AL. 582 TABLE 4 Efficiency comparison Topology Efficiency [9] 92.9% [11] 92.3% [12] 96.56% [13] 97.2% [14] 93.3% Proposed one 94.37% Comparison study of the multilevel topologies in terms of efficiency is shown in Table 4. A new single-source MLI topology based on SC cells was proposed in this paper. The presented SCMLI can generate high output voltage by a low input source with a reduced number of components and self-balancing capability. Another benefit of this converter is that it is capable of generating negative voltage levels without the need for high voltage switches. In the comparison conducted between the proposed converter and other similar converters presented in recent years, it is determined that the number of semiconductors and TSV in the proposed converter is less than in other converters. Finally, the experimental setup of the converter with 24-V input and 48-V output voltage amplitude (with 9-level) by 1 module is implemented and tested. The results show the proper operation of the proposed inverter. FIGURE 13 AUTHOR CONTRIBUTIONS Mohammad Amani contributed to the investigation, methodology, resources, software, supervision, writing the original draft, writing the review, and editing. Milad Niaz Azari contributed to the formal analysis, investigation, methodology, software, supervision, validation, writing the original draft, writing the review, and editing. Mohammad Rezanejad contributed to the formal analysis, investigation, software, supervision, validation, visualization, writing the original draft; writing the review, and editing. VDS (drain–source voltage) of switches both the switch voltage and current are non-zero. For simplicity, a linear approximation between the voltage and current of switches in the switching period is considered [12]. When the capacitors are connected in parallel for charging operation, the ripple losses occur by the difference between the respected input voltage and the voltage of capacitors. The ripple losses are calculated from the formula in ref. [14]. The conduction losses, switching losses, and ripple losses for a 4watt laboratory prototype are 1.31 × 10−5 , 5.934 × 10−3 , and 4.192 × 10−3 W respectively. According to the following equation to calculate the efficiency of the experimental prototype, the input and output power must be evaluated. Then based on Equation (6) the efficiency of the proposed topology is obtained 94.37%. ( 𝜂= Pout Pin ) × 100 (6) CONFLICT OF INTEREST The authors declare no conflict of interest. DATA AVAILABILITY STATEMENT Data sharing is not applicable to this article as no new data were created or analysed in this study. ORCID Milad Niaz Azari https://orcid.org/0000-0002-4191-8809 Mohammad Rezanejad https://orcid.org/0000-0002-5432759X REFERENCES 1. Vijeh, M., Rezanejad, M., Samadaei, E., Bertilsson, K.: A general review of multilevel inverters based on main submodules: structural point of view. IEEE Trans. Power Electron. 34(10), 9479–9502 (2019) 2. Narimani, M., Wu, B., Zargari, N.R.: A novel five-level voltage source inverter with sinusoidal pulse width modulator for AMANI ET AL. medium-voltage applications. IEEE Trans. Power Electron. 31(3), 1959–1967 (2015) 3. Franquelo, L.G., Rodriguez, J., Leon, J.I., Kouro, S., Portillo, R., Prats, M.A.: The age of multilevel converters arrives. IEEE Ind. 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Mohsenzadeh, M., Rezanejad, M., Adabi, J.: Marxiplier: an innovative Marx-based single source multilevel inverter with voltage multiplying capability. IEEE Trans. Ind. Electron. 69(1), 357–364 (2021) How to cite this article: Amani, M., Azari, M.N., Rezanejad, M.: Single source self-balanced switched-capacitor multilevel inverter with reduced number of semiconductors. IET Power Electron. 16, 575–583 (2023). https://doi.org/10.1049/pel2.12409
