Загрузил Алексей Кентов

OptSwTiming

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1
Optimal Switch Timing Circuit
with parasitics
DBOOT
CJDDRAIN
R1
K
J
DDRAIN
DOFF
CGDAUX
CDSGATE
CBOOT
+
-
PWM
A
CGSGATE
B
MGATE
K
E
R2
DON
F
CCOUPLE
+
-
CDSAUX
G
MAUX
R4
CGSAUX
QDIS
ZCLAMP
CJD1
H
D1
R3
DCLAMP
Confidential - Property of Technical Witts, Inc.
Optimal Switch Timing Circuit
•
•
•
•
Turns MAUX switch on at zero voltage without pre-trigger problems
due to drain diode parasitic capacitance.
Drain diode parasitic capacitance charges gate source
capacitance of MGATE during off transition and discharges gate
source capacitance of MGATE the same amount during on transition
thereby avoiding any pre-trigger switching power losses.
Fast gate discharge and negative gate voltage clamp for MAUX is
provided by QDIS and DON.
Positive gate voltage clamp is provided by ZCLAMP circuit for
consistent operation over a wide range of duty cycles.
Confidential - Property of Technical Witts, Inc.
2
3
Optimal Switch Timing Circuit
Turn Off Transition 1
R1
+
CBOOT -
PWM
CGDAUX
DOFF
A
E
CGSGATE
MGATE
K
F
R2
G
+ CCOUPLE
MAUX
R4
CGSAUX
QDIS
D1
•
•
•
•
•
Output of PWM (node A voltage) falls towards MAUX source voltage.
PWM current biases QDIS on.
CGDAUX and CGSAUX are discharged towards the MAUX source voltage.
D1 becomes forward biased holding gate of MGATE at source voltage of MAUX.
MGATE gate source voltage falls towards its threshold value but remains on until
MGATE threshold voltage is reached.
Confidential - Property of Technical Witts, Inc.
4
Optimal Switch Timing Circuit
Turn Off Transition 2
R1
CJDDRAIN
K
J
DOFF
+
CBOOT -
PWM
A
E
CGSGATE
F
CGDAUX
CDSAUX
G
+ CCOUPLE
QDIS
R4
CGSAUX
K
D1
•
•
•
•
•
•
MAUX gate source voltage is now below threshold so that node J voltage is rising
and CDSAUX and CGDAUX are charging and CGSAUX continues to discharge.
MGATE gate source voltage is now below threshold cutting off current in MGATE
channel. Channel current transfers to DOFF.
PWM (node A voltage) continues to fall and approaches source voltage of MAUX.
CGSGATE voltage continues to fall.
CJDDRAIN begins to charge as DDRAIN becomes reversed biased.
R4 current falls and reverses direction as node G falls through MAUX source voltage.
Confidential - Property of Technical Witts, Inc.
5
Optimal Switch Timing Circuit
Turn Off Transition 3
R1
K
DOFF
J
CJDDRAIN
CGDAUX
CBOOT
+
-
PWM
A
CCOUPLE
F + - G
E
CGSGATE
ZCLAMP
CJD1
•
•
•
QDIS
CDSAUX
R4
R3
Node A is at source voltage of MAUX.
Node K voltage rises above node A voltage driven by current from CJDDRAIN and R1
charging CJD1 and charging CGSGATE in opposite direction from enhancement.
R3, R4, and CGDAUX provide current to raise voltage of right plate of CCOUPLE,
R4 >> R3, IR3 ~ 1.3 mA, IR4 ~ 50 uA
•
QDIS remains on preventing node G and gate of MAUX from rising.
Confidential - Property of Technical Witts, Inc.
6
Optimal Switch Timing Circuit
Off State
DBOOT
DOFF
R1
+
CBOOT -
PWM
A
CCOUPLE
F + - G
E
CGSGATE
ZCLAMP
K
QDIS
R3
CJD1
•
•
•
•
•
MAUX is off.
CGSGATE continues to charge in opposition to enhancement.
CJD1 continues to charge, CJD1 << CGSGATE.
Right plate of CCOUPLE continues to rise in voltage.
CBOOT is replenished by DBOOT.
Confidential - Property of Technical Witts, Inc.
R4
7
Optimal Switch Timing Circuit
Turn On Transition 1
R1
J
CJDDRAIN
+
CBOOT -
PWM
A
CDSGATE
CGSGATE
K
CJD1
•
•
•
•
F
E
R2
DON
G
+ CCOUPLE
ZCLAMP
R4
CGSAUX
R3
PWM (node A) voltage goes high rapidly. Current drawn from PWM is small due to
high impedance of CDSGATE, CJD1, and CJDDRAIN.
Both source (node A) and gate (node K) of MGATE rise up rapidly with PWM signal,
VK > VBOOT.
Only a small amount of charge reaches CGSAUX. MAUX gate voltage remains well
below threshold voltage.
CGSGATE >> CJD1, only minor discharging of CGSGATE.
Confidential - Property of Technical Witts, Inc.
8
Optimal Switch Timing Circuit
Turn On Transition 2
R1
J
CJDDRAIN
CGDAUX
+
CBOOT -
PWM
A
CGSGATE
K
CJD1
•
•
•
•
F
E
DON
G
+ CCOUPLE
ZCLAMP
QDIS
CDSAUX
R4
CGSAUX
R3
Voltage on MAUX is collapsing discharging CGDAUX, CDSAUX, and CJDDRAIN.
CJDDRAIN discharge current pulls node K voltage down but not enough to enhance MGATE.
Current from CGDAUX pulls down gate of MAUX but voltage is clamped by QDIS and DON.
VNODEJ > VNODEK > VNODEA
Confidential - Property of Technical Witts, Inc.
9
Optimal Switch Timing Circuit
Turn On Transition 3
R1
K
CDSGATE
+
CBOOT -
PWM
A
CGSGATE
J
DDRAIN
B
MGATE
F
E
R2
CGDAUX
DON
+ CCOUPLE
CDSAUX
G
CGSAUX
R4
K
CJD1
•
•
•
•
Node J voltage has dropped below node K voltage forward biasing DDRAIN.
Node K voltage falls below threshold for MGATE enhancing MGATE and discharging CDSGATE.
Node B voltage rises to node A voltage.
DDRAIN current forces node K voltage to continue to fall towards source voltage of MAUX
further enhancing MGATE.
Node G voltage rises quickly towards threshold voltage of MAUX.
Confidential - Property of Technical Witts, Inc.
10
Optimal Switch Timing Circuit
Turn On Transition 4
R1
DDRAIN
J
K
+
CBOOT -
PWM
A
B
MGATE
•
•
F
E
R2
DON
G
+ CCOUPLE
MAUX
R4
CGSAUX
Node J voltage has dropped to source voltage of MAUX forward biasing MAUX body diode.
CGSAUX continues to charge through MGATE, which is now fully enhanced.
Confidential - Property of Technical Witts, Inc.
11
Optimal Switch Timing Circuit
Turn On Transition 5
R1
K
DDRAIN
DON
+
CBOOT -
PWM
J
A
B
MGATE
R2
E
CCOUPLE
F +
-
R4
ZCLAMP
H
K
R3
•
•
MAUX
G
DCLAMP
MAUX is fully enhanced.
ZCLAMP avalanches limiting MAUX gate voltage.
Confidential - Property of Technical Witts, Inc.
12
Optimal Switch Timing Circuit
On State 1
R1
K
+
CBOOT -
DDRAIN
A
PWM
J
B
R2
E
DON
CCOUPLE
F + - G
MGATE
•
•
•
•
MAUX
R4
MAUX and MGATE are fully enhanced.
DDRAIN holds gate of MGATE near source voltage of MAUX.
Output of PWM ~ VBOOT.
MAUX current ramps down towards zero.
Confidential - Property of Technical Witts, Inc.
13
Optimal Switch Timing Circuit
On State 2
R1
DDRAIN
K
J
I2
I1
+
CBOOT -
•
•
•
•
•
•
PWM
G
A
MGATE
R2
DON
+ CCOUPLE
MAUX
R4
Output of PWM is ~ VBOOT.
MAUX is fully enhanced.
DDRAIN holds gate of MGATE near source voltage of MAUX so that MGATE is fully enhanced.
I2 is limited by R1 to < 500 uA.
I1 is limited by R4 to < 200 uA.
MAUX current reverses and ramps up in opposite direction (shown).
Confidential - Property of Technical Witts, Inc.
Optimal Switch Timing Circuit Wave Forms
14
VPWM
VNODEA
time
0
VNODEK
0
time
VNODEB
time
0
VNODEG
0
time
VNODEJ
(compressed)
time
0
(all voltages are referenced to MAUX source voltage)
Confidential - Property of Technical Witts, Inc.
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